Intel Lead Timing Engineer in San Jose, California
As part of Intel, we will continue to apply Moore’s Law to drive the future of field-programmable gate array (FPGA) technology. The Programmable Solutions Group (PSG) has been delivering industry-leading custom logic solutions to customers since inventing the world's first reprogrammable logic device in 1984. In order to take advantage of the many opportunities that we see in the future for FPGA’s, PSG is looking for a great Lead Timing Engineer to join our team.
In this position, you will be responsible for all aspects of STA & timing closure activities of Intel PSG's FPGA in 14nm/10nm and below technology nodes. Your tasks will include but not limited to timing specification closure with Architecture/Software/IP Development teams, timing budget development, clocking, constraints development and timing closure. Develop novel ways to run STA analysis on some of the most complex silicon. Identify ASIC blocks and programmable routing logic partition and interact with Quartus team on building correct timing model for customer timing closure. Drive Silicon correlation effort between PrimeTime and Quartus Timing tools. Understand extraction issues, timing signoff corners methodology, design margins and quality checks. You will be part of the full chip timing team which is instrumental in driving timing closure and collateral required by Quartus team for customer timing closure.
BSEE, BSCE, BSCE, or related
8 years of semiconductor experience in CPU, SOC, ASIC, FPGA, ore related implementation and timing closure.
Experience scripting such as TCL/Python/Perl/Shell
Experience in RTL Development and physical implementation.
Experience with full chip timing closure and signoff using STA
Experience with Engineering Change Order (ECO) flows.
Expertise in STA signoff tools like Prime Time (PT), Constraint generation and verification tools like Static Timing Analysis (STA) and Fishtail.
Experience with process node and design interactions as they relate to target frequency and interaction with timing paths and resulting leakage and power trade-offs.
Experience in silicon characterization and timing correlation.
Experience with working across different levels of the organization (ie. cross functional teams, executive management, etc.)
Preferred (Additional) Qualifications
MSEE, MSCE, MSCS or related
Experience with the overall silicon development, such as RTL development, verification, and pre & post silicon validation.
Inside this Business Group
The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.
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